Thermal Impedance Monitoring during Power Cycling Tests

In this publication a new method of thermal impedance analysis of power modules is presented. It enables a distinction of different failure mechanisms within the heat flow path by electrical measurement during power cycling tests. With measurement and evaluation of the thermal impedance Zth the degradation can be located within chip solder layer, system solder layer and thermal interface material. 1 Motivation Reliability of power modules at power and thermal cycling load is determined by the deterioration of the heat flow path between die and heat sink or coolant. Up today during accelerated reliability tests this failure is detected by increase of the online measured quasi steady-state thermal resistance Rth. Thereby the increased Rth is caused by degradations in different layers of the heat flow path of the module between junction and reference temperature point, usually the case or heat sink temperature. By standard the failure criterion is a 20% increase of the initial value. The monitored trend of the Rth does not provide any information which layer degraded. Further, due to noisy measurement data, low variations of the thermal resistance caused by the deterioration of materials remain undetected. Therefore the failure analyses are performed subsequently with Scanning Acoustic Microscopy, X-ray or metallographic preparation to obtain more detailed information about the aging status of the power module. These analyses are time-consuming, several of them destructive and do not always deliver convincing analysis results. The monitoring of thermal impedance parameters promises a simpler and faster non-destructive analysis method for power modules during reliability tests. 2 Thermal Simulation First, the transient thermal behaviour of a typical power module with a base plate was simulated using equivalent CAUER-Network. The aim of this simplified model was to reproduce the effect of the failure within a specific material layer on the Zth(t) function. The basis of the simulation is a power module mounted on a liquid-cooled copper heat sink as depicted in Figure 1. Figure 1: Basis of Zth simulation, power module mounted on a liquid-cooled copper heat sink Each layer of the heat flow path was simulated by two thermal resistances and one thermal capacity. Thereby the thermal spreading was simplified and considered an angle of 45°. The heat flow area increases accordingly along the heat flow path from chip towards coolant. The equivalent circuit of one PCIM Europe 2011, 17 – 19 May 2011, Nuremberg, Germany Paper 39 ISBN 978-3-8007-3344-6 © VDE VERLAG GMBH ∙ Berlin ∙ Offenbach 241 single material layer is depicted in Figure 2 (left), the total thermal system is depicted in Figure 2 (right). Figure 2: CAUER based thermal circuit for simulation of different failures Values of thermal resistances and capacitances of the whole thermal system were calculated with the typical power module data presented in [1]. The chip area was about 2 cm2. The temperature dependency of material properties was neglected. The thermal impedance is calculated between the chip and the coolant accordingly following equation (1). The coolant temperature is assumed constant and represents the reference point Tref. Z (1) With the simplified simulation model three typical failures were investigated: degradations of chip solder layer, system solder layer and thermal grease (TIM). For each type of failure the area of the corresponding layer was reduced in order to increase the whole thermal resistance between junction and coolant by 20%. The result of this simulation is shown in Figure 3. This result shows that different failures lead to different Zth curves. Different time points for the splitting of the curve with failure from the curve without failure can be distinguished. In [2] this effect was used experimentally to observe chip solder layer degradation of high power modules during power cycling tests. Zth values were measured at two different time points. Thereby the chip solder layer failure could be distinguished from the thermal grease effect. The separation of the system solder layer failure from the chip solder layer was not possible with this method. Figure 3: Simulated Zth curves of different failures The Zth(t) function is usually described using equations (2) and (3), which represent the equivalent FOSTER-network (Figure 4 left). Z t R 1 (2) τ R ∙ C (3) In data sheets for the Zth(t) function mainly four or five RC elements are used. It is sufficient for an acceptable approximation of a real measured thermal transient curve. The equivalent FOSTER-circuit can be used for the proper calculation of the whole given thermal system. The nodes between RC elements of this circuit do not refer to specific geometric points of the thermal system [3]. Therefore with this network a physical interpretation of partial thermal areas within the heat flow path is not possible. The correct physical description of partial thermal resistances gives the equivalent CAUER network as seen in Figure 4 (right). However, this circuit cannot be extracted directly from the measured Zth(t) 0,00 0,05 0,10 0,15 0,20 0,25 0,30 1,0E-04 1,0E-03 1,0E-02 1,0E-01 1,0E+00 1,0E+01 Z th in K /W time in s without degradation chip solder layer system solder layer thermal grease 45° PV Tcoolant chip solder layer Cu heat sink PCIM Europe 2011, 17 – 19 May 2011, Nuremberg, Germany Paper 39 ISBN 978-3-8007-3344-6 © VDE VERLAG GMBH ∙ Berlin ∙ Offenbach 242 function, since many solutions are possible. In order to obtain a CAUER-network, first, the equivalent FOSTER-network has to be extracted from the Zth(t) curve. After this, with the network transformation the equivalent CAUER network can be calculated. At that the number of RC elements is equal in both equivalent circuits. Figure 4: Equivalent networks for description of thermal systems The approach for the localisation of different failures within the heat flow path of a power module is the monitoring of CAUER ri parameters. The schedule of this method is as follows: • Measurement of the Zth(t) function • Extraction of the equivalent FOSTER network with an approximation method (e.g. [4]) • Transformation of FOSTER into CAUER equivalent circuit (e.g. [3]) • Monitoring of CAUER ri parameters First, this method was verified with the simulation data. With the method of [4] the Zth(t) curves from Figure 3 were approximated with the equation (2). With eight elements the best fit could be reached. After the approximation the FOSTER-network was transformed into the CAUER-network. For this transformation the method of the recursively rapid FOSTER-CAUER circuit transformation was applied described in [3]. The partial CAUER thermal resistances of simulated failures are compared in Figure 5. Obviously, for a specific failure only one partial thermal resistance has a significant increase in comparison to the ri values without degradation. Other elements remain nearly unchanged. These points are marked with arrows. Figure 5: Partial thermal resistances of CAUER circuit, results of simulated failures A ri element cannot be referred to a certain material layer, since the number of extracted RC elements does not correspond to the number of layers. However, CAUER elements indicate specific physical area within the heat flow path. Thereby the ri order relates to the direction from chip to coolant. The correlation of ri to a specific part of the heat flow path can be estimated by comparison between extracted CAUER ri and Ci values and values of the known real power module package. In summary, it can be stated that the monitoring of CAUER-parameters can be a possible method for the separation of different failures. 0,00 0,02 0,04 0,06 0,08 0,10 0,12 0,14 1 2 3 4 5 6 7 8 R i n K /W ri Without degradation Thermal greace degradation System solder degradation Chip solder degradation R1 Rn C1 Cn PV FOSTER network r1 rn c1 PV cn CAUER network PCIM Europe 2011, 17 – 19 May 2011, Nuremberg, Germany Paper 39 ISBN 978-3-8007-3344-6 © VDE VERLAG GMBH ∙ Berlin ∙ Offenbach 243 3 Experimental Results The monitoring of CAUER ri parameters was investigated experimentally with a superimposed power cycling test. The device under test was a standard power module of the manufacturer Infineon Technologies AG as shown in Figure 6. For the test the power module was mounted on a liquid-cooled copper heat sink. With an external heating/cooling station the power module was heated and cooled passively. During heating phase power cycles were superimposed. Test parameters are shown in Figure 7. The maximum junction temperature and maximum case temperature are beyond the specifications of this power module type. Figure 6: DUT (standard power module), Test set-up Tcoolant_min 22°C Tcoolant_max 122°C theating (passive cycle) 10min tcooling (passive cycle) 5min ILoad 220A ton (power cycling) 2s toff (power cycling) 4s Power cycles per passive cycle 100 Tjmax 175°C ∆Tj (power cycling) 53K Figure 7: Test parameter of superimposed power cycling test During the test the thermal impedance was measured periodically every 20 passive cycles. For this measurement the cycling test was interrupted at the lowest coolant temperature at the end of the cooling phase. After that a load pulse was applied with 250A load current, 30s heating and 30s cooling time. The Zth(t) was measured between junction and case during the cooling phase. The junction temperature was measured with the VCE(T)-method described in detail in [5]. The case temperature measurement was realised with a thermocouple beneath the active chip area as shown in Figure 6 (right). The power losses of the IGBT were measured at the end of the heating phase. The Zth(t) was determined according equation (1). After that, the equivalent FOSTER circuit was approximated with the least square fit method. The best fit corresponding to the equation (2) could be reached with four RC elements. In comparison to simulation result less elements were sufficient. The measured thermal impedance Zth(t) of IGBT 21 and the result of the mathematical approximation are shown in Figure 8. Finally, the CAUER elements were calculated with the circuit transformation algorithm from [3]. The partial CAUER ri elements were monitored during the test. The trends of these parameters are seen in Figure 9. 0 20 40 60 80 100 120 140 160 180 200 0 200 400 600 80